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DNL and INL simulation time

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Member level 5
Aug 4, 2004
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inl r-string dac

Hi, I am trying to get the DNL and INL for my 12-bit SAR ADC. The problem is that each sample takes abt 2 hours simulation time. Does that mean I have to spend 8000 simulation hours to get the DNL and INL plotted? It sounds absurd to me. May I know am I doing it the correct way and what is the normal practice to simulate the DNL and INL for ADC? Thanks

sar adc simulink

I am also in this field and have given a lot of thouhgt to it. But couldn't find a better way. Theoritically, if you could model the whole circuit in verilog-a or in some thing lese which ate least can take care the issues related to INL/DNL; you can go with the model. But what I found is that it is very tought ot do the modeling correctly; at least for the whole ADC containg linear/non-linear/clock driven blocks.

You may do one thing. You could give some step inputs; i.e.; stare case. The values sould cover throughout the commonmode range but not all the steps. Thus you will be getting maximum data and others; those are still missing could be interpolated. But this is not at all correct method. Just a method to get the idea about the whole picture.

I don't know which simulator you are working with. From my experiance what I got is that when both analog and digital parts are simulated in an analog simulator (for me Cadence); it takes a lot lot time. The major part is taken by the digital cells. If you are enough confident that your digital part is pretty fine and not sensitive to clock jitter, clock edge etc (i.e. actual system speed is much less than the individual gate or FF speed and are used relaxedly); then you can do the following.
--> you replace your digital parts by ideal components from analog lib/ ahdl etc. These will save your simulation time.

I want to add one point here. You must check very carefully before taking any of the other. What I told is what I suppose. Neither of them is being folloed by me; as I am yet to complete the whole ADC. I would even request that; if do some thing efficient; you post it for other poor guys like us.

Gd Luck..

simulink for adc-sar

You may model the DAC you're using in mathlab, and simply add mismatches in mathlab. That way, you will be able to know the linearity of your dac, which should be very close to that of your SAR ADC. Mathlab modelization will be far faster than spice one.

There are also many ways to estimate your INL/DNL as a function of you're devices mismatch:

ex: for an N bit Resistor String DAC
INL=2^(N-1) ΔR/R

So you just have to size your device in function of your desired linearity.

sar adc+simulink

Thank you all for the suggestion. Can anybody please provide me some materials on how to simulate capacitor array DAC in simulink? I do not know how to implement the switching algorithmn in simulink. Thanks.

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