xilinx pcie core
sbob, thanks a lot.
I know the PCIe is a bi-directional "always ready" bus, but the memory is shared by all the devices. How can the PCIe device write the memory as possible as it can? I am confused. Whether the "Root" can help to do that?
Added after 8 minutes:
By the way, Can I understand the DMA write steps as following:
1. Memory write or IO write address, length and so on registers.
2. Memory write or IO write "run" register to make the "DMA write handle" module to work.
3. When the DMA write work is done, the interrupt is set up to inform the logic core to send out the interrupt information. And the driver receive the interrupt and do some memory copy.
Is my understanding right?
I am using the PIPE Endpoint 1-lane Core v1.3. In the core's configuration interface, there are two signals: cfg_interrupt_n, cfg_intr_rdy_n. I think, when the cfg_interrupt_n is low, the core will send out the correct interrupt and when the "message" is sent out, the core will set the cfg_intr_rdy_n to low? But how can the core know which interrupt(INTa, INTb, INTc, INTd) will be triggered?