Dividing large bit numbers in verilog (spartan 3e)

[user_asic]

Division is not one of the easiest functions to implement in digital systems. However I have a system which will be dividing very large bit numbers in excess of100 bits. The cores provided by chipscope cannot handle this sort of large scale division. How to tackle this issue?

 

[headup]

u must read more about division - the successive methods in FPGA are not so much. i develop my own full pipelined divider (non-restoring algorithm), but if u want to use more than 16/8 bits the delay between carry in-carry out of SLICEs is too big and the speed decrease (may be under 150Mhz). If u want to divide big numbers - look around for some other decision of your basic alogrithm without division (or something based on >> ) or think for z = x . (1/y) , where 1/y is from look-up table with some error of coarse. the task is realy hard. u was posted your questions about some code in forums.xilinx.com (synthesis board), or i'm wrong?

 

[user_asic]

Well I need to approximate the golden ratio by using fibonacci numbers. As you now, these numbers get extremely large. I know of no other way to do this. And yea, I also asked a few questions over at Xilinx.

 

[mux_master]

100 bits seems like an extremely large number. But, if this is required for your application I am guessing you are going to have design your own divider circuit. I am guessing any of the standard divider circuits can be scaled up.