u must read more about division - the successive methods in FPGA are not so much. i develop my own full pipelined divider (non-restoring algorithm), but if u want to use more than 16/8 bits the delay between carry in-carry out of SLICEs is too big and the speed decrease (may be under 150Mhz). If u want to divide big numbers - look around for some other decision of your basic alogrithm without division (or something based on >> ) or think for z = x . (1/y) , where 1/y is from look-up table with some error of coarse. the task is realy hard. u was posted your questions about some code in forums.xilinx.com (synthesis board), or i'm wrong?