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# Divide clock by 3 at 30 MHz ????

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divide clock

Hello,

anyone knows a simple way how to divide frequency by 3 ?

The whole problem is as follows...

I have a TTL compatible signal with the frequency of 10 MHz. I need to multiply the frequency by 3, because I need 30 MHz as an input to AD9851 DDS chip.

So, I designed a simple PLL multiplier (NE564) and I need "divide by 3" circuit in the loopback.
I tested a simple synchronnous divider with 2 D-flipflops (74HC74) and one NOR, but setup time and propagation delay is too long for 30 MHz.

Anyone have some idea how to do it ? Or which logic family is able to work correctly at 30 MHz in this circuit ?

I do not want to use ECL chips, I would like to be able to do it with normal HCMOS/TTL chips.

Thx for any help

how to divide 30 by3

If you want to multiple your 10MHz signal to 30MHz, a simplest way
instead of using a PLL exist.
In your 10MHz rectangular signal spectrum you already have 30MHz at minus 10dB (approximately 3 times) below than fundamental. You must add a bandpass filter, tuned at 30MHz and an amplifier (74HC04 inverter, biased at active region with the aid of a feedback resistor) and an additional 74HC04 after the amplifier. You can use inverters from AHC series, LCX series too - they are faster than HC.
Take a look at Wenzel Associates web site. You'll find some useful info
there. If you need example schematic, PM me.

Best regards,

STO

divide-by-3 schematic

umm, if you want you can use two flip-flops connected like so:

node f----| D QB | ----- | D Q | ---- node f

with the clock not shown. This gives a divide by three. But the duty cycle is not 50%. If your pll uses a pfd (edge triggered) this isn't a problem. But if it uses a multiplier or xor, then its a pain. So then you have to put a multiply by 2 in front of this, and then an asynchronous divide by 2 after. The multiply by 2 is just a delayed version of the input and the input through an xor gate. The divide by 2 is just a flip flop with its D input tied to its output QB.
Hope this helps.

counter to divide clock

why not use 74AC74? it should be fast enough.

74ac74 multiplier

you can use a simple pld with a synchronous counter modulo three.
send me a message if need vhdl description,bye Stark

74hc74 divider 3

Thx a lot.

I will use the 74AC74, it seems as a simple solution.

divider by 3

You don't need any PLL to do this simple job.
Just a bandpassfilter followed by an inverted 74hc04 should do the job. You can also use a smith trigger like 74ac14 after the filter....
If you really want a divider I would tell you to use a programable counter like 74hc193 programmed to count down and load with a preset value of 3.
The 2 dff 74ac74 cascaded will also work, I have already tested it. But unfortunatly all the solutions using dividers will give a duty cicle different than 50%.
Maybe if you multiply and divide by an even number like 6 you can get rid of this problem....
Greetings to all you
S.

sinatra: I know about the problem with duty cycle. I forgot to mention that I am using div 2 (from 10 to 5 Mhz) and after div 3 counter, there will be div 2 in the loopback (total div 6 50% duty cycle).

The idea with the third harmonic is interesting. I will try to design and test the filter and I will see...

Re: another solution

Stark said:
you can use a simple pld with a synchronous counter modulo three.

modulo 3 is not synthesizable .. do u have any work around ?

Omara007 - don't use the modulus operator. Most synthesis tools are too dumb to divide by anything but powers of two.
Instead, build a simple counter that goes 0, 1, 2, 0, 1, 2, ... by using some other arithmetic. If you aren't sure how to do that, tell us which language you are using, and someone can show you an example.

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