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# Divide by 3 counter with 75 % duty cycle

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#### nisheethg

##### Newbie level 1
hello
i am preparing for interviews and have come across a question which is
Divide by 3 counter with 75 % duty cycle

For 75 % duty cycle i need to count 1/4th of a cycle...how do i do it??

Any clues...

its very simple just build divide by 3 counter and invert any one of its output
to get 75% duty cycle!
Here is one more way! example in verilog!
Code:
module div3_75 (
// Outputs
clk_out,
// Inputs
clk, reset_n
);
input clk, reset_n;
output clk_out;
reg [1:0] count;
assign    clk_out = count[1];
always @(posedge clk or negedge reset_n) begin
if (!reset_n)
count <= 0;
else
count <= { ~count[0], ~count[0] & count[1]};
end
endmodule

Hi nand_gate this is not 75% duty cycle.

it is 66% duty cycle, as output is high for 2 clok cycles and low for 1 clock cycles..

how to do 75%, could u tell me plz.

OK!
What you need is 2x clock multiplier.

Code:
                                   +------+
+----------+    |      |
+----+  | +----+   |    | div  |
clk in    |    |  +-|   q|---(----|> by  |----+
----+----| 2x |----0>   |   |    |  3   |    |
|    |    |    |  qn|---+    |      |    |  ___
|    +----+    +----+        +------+    +--\  \
|                                            )  )--- div by 3
|                            +------+    +--/__/   75% duty cycle
|                            |      |    |
|                            | div  |    |
+----------------------------|> by  |----+
|  3   |
|      |
+------+

first make a divide by 3 with 50% DC . Then delay this o/p by 25% . OR the two signals you will get the desired o/p.

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