Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

distributed power amplifier

Status
Not open for further replies.
P

padoh

Junior Member level 2
Junior Member level 2
Joined
Jul 2, 2012
Messages
21
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Visit site
Activity points
1,458
ive designed a distributed LNA..but as i place the input coupling cap of 50p or greater or infact any capacitor at the i/p, my gain becomes negative? can anyone plz suggest where is the problem in the design? the o/p coupling cap works fine
 

Present a schematic and specify frequency range of your input signal. Otherwise it's just guessing?
 

johnjoe said:
Present a schematic and specify frequency range of your input signal. Otherwise it's just guessing?
Click to expand...

its kind of confidential..can u just specify some of the reasons tht might be the causes.. frequency from 100M to 2G..plz it would be a great help..m just stuck up..
 

Ok, which technology, bipolar or mos? Or maybe it is possible that you roughly depicts the input stage not the complete lna? What happen if you use smaller values for your cap?
 

johnjoe said:
Ok, which technology, bipolar or mos? Or maybe it is possible that you roughly depicts the input stage not the complete lna? What happen if you use smaller values for your cap?
Click to expand...

CMOS 130nm..i just applied a 500f cap n even then the gain is negative ..upto several micros of capacitance, the gain is still negative..its a three staged cascoded DA with inductive degenration..a transmission line at the input..

- - - Updated - - -

ive attached a ppr..plz see fig2..my design is almost the same( the input path connecting the lower transistors of the cascode)..i am just missing the capacitor Cb..what effect can this have on the circuit gain?

- - - Updated - - -

ive attached a ppr..plz see fig2..my design is almost the same( the input path connecting the lower transistors of the cascode)..i am just missing the capacitor Cb..what effect can this have on the circuit gain?
 

Attachments

  • payam heydari...distributed lna2007.pdf
    1.4 MB · Views: 80

Are you blocking maybe some dc bias voltage at the gate, despite I don't see any bias in fig.2, but maybe in your design! And be careful with uploading ieee documents, i think it is not allowed.
HTML:

---

Now I see on the right side some dc path, again: are you blocking maybe this voltage?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top