hello! i have this code :
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY display IS PORT (
Column,Row: IN STD_LOGIC_VECTOR(9 DOWNTO 0);
Red,Green,Blue: OUT STD_LOGIC);
END demo;
ARCHITECTURE Dataflow OF display IS
BEGIN
-- Red boarder
Red <= '1' WHEN
(Row(9 DOWNTO 0) = "0000000000") OR -- rows 0
(Row(9 DOWNTO 0) = "0111011111") OR -- rows 479
(Column(9 DOWNTO 0) = "0000000000") OR -- columns 0
(Column(9 DOWNTO 0) = "1001111111") -- columns 639
ELSE '0';
-- Green small square
Green <= '1' WHEN
((Row(9 DOWNTO 4) = "011000") AND -- use only the first 6 most
(Column(9 DOWNTO 4) = "001000")) -- significant bits giving a
ELSE '0'; -- 16 x 16 pixel square
-- Blue letters "E C"
Blue <= '1' WHEN -- this is just setting
-- Blue to 1 when any one of the following conditions is true
((Row(9 DOWNTO 4) = "001000") AND
((Column(9 DOWNTO 7) = "001") OR (Column(9 DOWNTO 7) = "011"))) OR
((Row(9 DOWNTO 4) = "001001") AND
((Column(9 DOWNTO 4) = "001000") OR (Column(9 DOWNTO 4) = "011000"))) OR
((Row(9 DOWNTO 4) = "001010") AND
((Column(9 DOWNTO 4) = "001000") OR (Column(9 DOWNTO 4) = "011000"))) OR
((Row(9 DOWNTO 4) = "001011") AND
((Column(9 DOWNTO 4) = "001000") OR (Column(9 DOWNTO 4) = "011000"))) OR
((Row(9 DOWNTO 4) = "001100") AND
((Column(9 DOWNTO 7) = "001") OR (Column(9 DOWNTO 4) = "011000"))) OR
((Row(9 DOWNTO 4) = "001101") AND
((Column(9 DOWNTO 4) = "001000") OR (Column(9 DOWNTO 4) = "011000"))) OR
((Row(9 DOWNTO 4) = "001110") AND
((Column(9 DOWNTO 4) = "001000") OR (Column(9 DOWNTO 4) = "011000"))) OR
((Row(9 DOWNTO 4) = "001111") AND
((Column(9 DOWNTO 4) = "001000") OR (Column(9 DOWNTO 4) = "011000"))) OR
((Row(9 DOWNTO 4) = "010000") AND
((Column(9 DOWNTO 7) = "001") OR (Column(9 DOWNTO 7) = "011")))
ELSE '0';
END Dataflow;
this VHDL code generate a red border, two blue letters (“EC”), and a green square.
I want to change this code. instead of "E C" to display "LICENTA 2012." Can you help me? Thank you!