dispaly Binary in 7seg ! with Excess-3

[crazy-igzp]

I have a binary output (8-bit); and I need to display them on 2 7seg! one of my prof told me that I can use Excess-3 code to do it ! I just know that the ex-3 it's just binary + 3 ! and it's self-complementing "0+9=1111" etc .. ! so any idea how to use it to display in 7seg ?

 

[mrflibble]

https://bit.ly/1fesBtD

 

[shahulakthar]

I hope this example help you better understand.

**broken link removed**

 

[ads-ee]

You can't display a 8-bit binary value (0-127) on two (2) 7-segs. You need three.
https://en.wikipedia.org/wiki/Excess-3
your prof is wrong.

 

[crazy-igzp]

You can't display a 8-bit binary value (0-127) on two (2) 7-segs. You need three.
https://en.wikipedia.org/wiki/Excess-3
your prof is wrong.

he told me to use ex-3 code , (2 7seg) that was my choice cause the max number that i want to disply is 64 ! that's why I did chose 2 7seg !
and ! I already know the logic !, read about it but the probleme is how to use it in converting from binary to (7seg code) !

 

[mrflibble]

You can't display a 8-bit binary value (0-127) on two (2) 7-segs. You need three.
https://en.wikipedia.org/wiki/Excess-3
your prof is wrong.

That, or there is the ever popular error in translation. 8-bit value displayed on two 7 segment displays should be no problem. That is just a single 4-bit nibble displayed on each of the 7-segment display. As in, you just display one hex digit per display. Been there done that. Quite handy during simple debug. Didn't use any excess-3 stuff, just regular case statements in verilog.

But if you are only allowed to display 0-9 digits then of course you are right that the possible values are 00-99, for which you only need a 7-bit representation.

 

[crazy-igzp]

That, or there is the ever popular error in translation. 8-bit value displayed on two 7 segment displays should be no problem. That is just a single 4-bit nibble displayed on each of the 7-segment display. As in, you just display one hex digit per display. Been there done that. Quite handy during simple debug. Didn't use any excess-3 stuff, just regular case statements in verilog.

But if you are only allowed to display 0-9 digits then of course you are right that the possible values are 00-99, for which you only need a 7-bit representation.

case statement , it will be long writing it for every single binary form 0 to 64 ! and ! I cant change the fact that they are 8 bit , cause I'm not working only on displying ! it's first start with multiplying 4 bit
(4-bit)*(4-bit) ===> ( 8-bit ) , and display it !
I dont wana write a code that long !

 

[ads-ee]

So you are displaying in decimal from the 8-bit binary value with the maximum value of 64?

Why would the prof suggest using excess-3 to display the value...64 is only 2-digits...or is that one of the undefined requirements that you neglected to state explicitly.

you could code the case statement such that you only have 10 possible cases i.e the digits 0-9 on a 7-seg display. Each case statement has multiple matches that produce that 7-seg driver value for that digit. Two such case statements would make up the upper digit and the lower digit on the 7-seg displays. Now you don't have to write 128 lines of code...only 20 ;-)

regards

 

[mrflibble]

case statement , it will be long writing it for every single binary form 0 to 64 ! and ! I cant change the fact that they are 8 bit , cause I'm not working only on displying ! it's first start with multiplying 4 bit
(4-bit)*(4-bit) ===> ( 8-bit ) , and display it !
I dont wana write a code that long !

Except that I said, well what I already said. You know what a nibble is? 4 bits. As in 0-F value. You can display that on a 7-segment display. 2 nibbles = 8 bits, you can display that on two 7-segment displays. You only need to write one module with 16 case statements (cases 0x0 to 0xF). Then instantiate that twice, and you have your 8-bit in ==> two segment displays out.

And in the probable case that you should be displaying only 0-9 digits, well then it is only 10 case statements. Isn't module instantiation wonderful?

But never mind all that. Step one: walk to prof. Step two: ask for clearer problem description if you are in doubt as to what the assignment is. Easy question: what should we display when the multiplication result is larger than what can be displayed on the 00-99 display?

 

[crazy-igzp]

So you are displaying in decimal from the 8-bit binary value with the maximum value of 64?

Why would the prof suggest using excess-3 to display the value...64 is only 2-digits...or is that one of the undefined requirements that you neglected to state explicitly.

you could code the case statement such that you only have 10 possible cases i.e the digits 0-9 on a 7-seg display. Each case statement has multiple matches that produce that 7-seg driver value for that digit. Two such case statements would make up the upper digit and the lower digit on the 7-seg displays. Now you don't have to write 128 lines of code...only 20 ;-)

regards

I did not understand !

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Except that I said, well what I already said. You know what a nibble is? 4 bits. As in 0-F value. You can display that on a 7-segment display. 2 nibbles = 8 bits, you can display that on two 7-segment displays. You only need to write one module with 16 case statements (cases 0x0 to 0xF). Then instantiate that twice, and you have your 8-bit in ==> two segment displays out.

And in the probable case that you should be displaying only 0-9 digits, well then it is only 10 case statements. Isn't module instantiation wonderful?

But never mind all that. Step one: walk to prof. Step two: ask for clearer problem description if you are in doubt as to what the assignment is. Easy question: what should we display when the multiplication result is larger than what can be displayed on the 00-99 display?

the result can't be larger than 64 ! 64 is the max ! I'v allready told that ! it multiply 4bit*4bit but I forgot to mention that they are 4 bit signed ! so the big multiplication will be -8*-8 so !

I've never hear about module instantiation in VHDL ! how it work ?

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need exemmple if possible !

 

[mrflibble]

Mystery solved then. Time for 1) using a dot to denote a negative result and 2) reading your course material on how to instantiate modules. Or use google.

Random google hit to pre-empt the predictable:
https://www.doulos.com/knowhow/vhdl_designers_guide/components_and_port_maps/