Discussion: The importance of having 50% duty cycle

[no_mad]

Hi all,

Please share ur experience, ideas, thought or etc on this topic.

In my opinion, the 50% duty does not affect much, unless you are using phases as opposed to edges. That would be the case where you are using level-sensitive devices as opposed to edge-triggered ones.

An example that comes to mind is pipelining using latches. You could possibly run into problems in that case.

bansalr wrote:
"The only problem if u don't have 50% duty cycle when timing is evaluated between negative edge and positive of the same clock. because the margin will be less in one of the case when duty cycle is not 50%.

others plz share. "

Thanks bansalr

 

[haytham]

Hi
I agree with you
IF your design is edge triggered, then duty cycle is not importnat
While if it is level triggered or phase info is important some how to the designer, then duty cycle info is imoprtant.

thanks

 

[newcpu]

If you just use single triggered edge, the duty cycle is not important.

 

[leeenghan]

Hi,

To be complete, duty is not important if

1. you do not use both the edges
2. there is not min-cycle violation due to change in duty cycle.

Regards,
Eng Han
www.eda-utilities.com

 

[silencer3]

but if u have some latches in ur design, then time borrow will change based on ur duty cycle effecting ur timings.

If u r operating ur design at very high frequencies, then duty cycle can have impact as clock uncertainty can play a role

 

[Thinkie]

If your design is 100% synchronous, you never use negative-edge and the duty cycle is long enought not to cause a min width violation , then you are ok.

We have designed some chips are with 33% duty cycle due to a x3 clock multiplier and everything was ok

 

[Shohdy]

Hi,

I think that discussing a subject like this can not go alone, it should be accompained by the intended application or design.
That's to say we should discuss if a 50% duty cycle is important or not in a certain design or application...not generaly as we are doing, cause in a some suitiations it may be important and in others it may be not.

Regards,
Shohdy

 

[hys]

A few points here....

1. In case of a fully synchronous designs with use only single clock edges (either rising or falling edge), there should not be any problem, provided sufficient design margins are allocated in the timing paths.

2. If timing is met (STA) with stringent constraints and very less or no margins, then there might be a problem even if it is a single edge based design. During manufacturing we need to have provision for slow-process and fast-process effects.. due to which the rise time and fall times of signals may vary. In such cases say if we are using rising edge and due to slow-process the rise time has increased (10% to 90% rising of a signal) then the rising edge is detected slightly later than usual => edge detection happens late => and the following logic gets very less time to provide result before the next edge.

So inorder to take care of such scenarios generally 50% duty cycle is preferred (because u dont know which of tr (rise time) or tf (fall time) may be affected. This keeps it even probability in either case...


Best Regards,
Harish
https://hdlplanet.tripod.com
https://groups.yahoo.com/group/hdlplanet

 

[semi_jl]

Hi, everyone,
I think the description of "hys" is very accurate and detailed. The duty cycle is not key in single edge design, but you must prevent the negative delay.