Hello KODE:
Thank you for your insights.
Here is my flowchart for FPGA implementation. Assuming that the RTL written is synthesisable and fully tested in simulation! Hehe!!!!
Point 1 -Synthesis without timing constraint
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Ok, I could understand that synthesize a design with simply providing the global clock frequency may be sufficient (i.e., no timing constraint [may not the correct term, but you know what I mean!] is provided upfront to the synthesis. Following specifying the global clock, you can begin to compile and synthesize your design in the EDA synthesis tools. Looking at the report after the completion of the synthesis run, you may have circuit that meets your desired operating frequency. Great.
If design falls apart during synthesis (failing in meeting the desired operating clock with setup/hold violation), GO to Point 3 and uses timing constraint to optimise the design (not functionality!) so that it meets timing closure. Succeeding Point 3, you can then proceed to Point 2.
Point 2 -Importing EDIF into FPGA Vendor tools for Place&Route (i use the =====
term FPGA implementation).
After successfully synthesizing our design (without timing contraint), you can be begin to Place and Route the circuit inside the target FPGA technology. ONE QUESTION: do i need to specifying any timing here? I am thinking only about pin allocation, and nothing else. Since I have specify the global clock of my design during the synthesis process flow. Anything that I missed???
At the end of Place & Route, if the design meets requirements,; i.e, no negative SLACK TIME. SUPERB. You may then proceed to FPGA bitfile download to check if the design ACTUALLY works. ONE QUESTION HERE: If the the final design passed the Place & Route stage with no error, is the design bound to works (maybe not perfectly since there may be some corner cases which may not fully accounted in the simulation of the design).
Point 3 - Further Improvement on "Working" Design
To further improvement (as all Engineers do) the design so that it uses less logic and runs faster, you could achieve these improvement through the usage of timing constraint.
Reading XILINX technical note, it is suggested the circuit design performing better (with timing contraint applied). Reasons are that the combinational (combinatorial) logic between registers are optimised (in order to meeting user timing constraint). HOWEVER, the design functionality is NOT COMPROMISED. It is noted (using FPGA floorplan viewer) that design that uses timing contraint have its related logic closely packed and placed closer to the I/O pin to minimise delay, in constrast to the rather "loosely" placement of related logic (design with no timing constraint) inside the FPGA chip.
What are your thoughts???