T
The waveform shows Vgs of the fet.Can't see on the schematic, the node numbers to tell what
the waveform plot is showing.
The problem is the top post is an intrinsic problem of this type of dc restored transformer gate drive...and there is no way to get rod of this problem without ridiculously large amounts of damping resistance......unless someone has an as yet unknown fix?....I don't think it depends on the speed of the feedback loop, other than it being possibly worse with slow feedback loops.it's possible that a slow loop with bad error amp overshoot
might act badly.
The problem won't occur with slower duty cycle variation. If you have both, large duty cycle range, e.g. 0 to about 90 % in your example, and fast d.c. variation, the simple DC restoring circuit can't work.I don't think it depends on the speed of the feedback loop, other than it being possibly worse with slow feedback loops.
Yes, reminds me to the fact that you get paid for designing suitable circuits to deal with this conditions, not we.It is MWD application, and we cant use optos due to 170degc ambient
It is MWD application, and we cant use optos due to 170degc ambient
You're not wrong, but who has the time and resources to spend vetting a component beyond its specifications for a single contract? That's why designs like this are best left to companies who deal with these design challenges specifically. They must have a list of components whose operation at high temperature has been studied rigorously; information they keep for themselves.Similar to other complaints, which seem to come from a
literal reading and belief in the comprehensive truth of
datasheets. But what makes an optoisolator unusable
at "high" temp? 170C is not particularly high, a BJT is
going to leak some and saturate worse but not just die
abruptly at 125.1C; LED neither. Maybe your barrier
glop decomposes but I'd doubt that too. Have you shown
that there is not one opto that can, with proper design,
do the job? Or are you just letting paper hold you back?
Thanks, yes it is now obvious, but there seems to be no alternative.Is the source of the simulation failure not obvious?
thanks but please tell where, because I have never seen this described anywhere, ever.Yes, the DC restoration circuit has problems with fast changes in duty cycle. This is a well known issue which I've always seen described in app notes
Get payed? Is there money in Fracking? I don't think so.Yes, reminds me to the fact that you get paid for designing suitable circuits to deal with this conditions, not we.
I know the classic unitrode app notes cover it.thanks but please tell where, because I have never seen this described anywhere, ever.
It's part of the physics of how a transformer works. The standard solution is to use an actual gate driver with an isolated power supply, and use an optoisolator for signal isolation. Even for signal isolation, 0-95% probably isn't feasible for a transformer, unless you use a more sophisticated modulation scheme using narrow trigger pulses (like how is done in some monolithic gate driver ICs).To think, in 2015, the SMPS fraternity does not have an answer for a reliable high side gate transformer fet drive that can do 0 to 95% duty cycle, and go to zero duty cycle without this potentially massively destructive problem.
Thanks, though as you know, with a buck converter, there is no nice leakage L to slow up the rise of current which charges up the fet CDS.......and thus in a buck in CCM, as soon as the high side fet turns on, the entire input voltage...in this case up to 400v, is available to slam the fet VDS from 0v TO 400v in very quick time....greater than 50v/ns, which violates the transient immunity dv/dt of these kind of signal isolator chips which run the gate drive signal up to the high side fet drive.The standard solution is to use an actual gate driver with an isolated power supply, and use an optoisolator for signal isolation
Thanks, but seems a bit unusual (hope its not a windows problem), I just downloaded it from the top post and it works fine for me….the load goes no-load at 3.5ms. By the way I use the “Alternate 2” solver and the “modified trap” thing, (in the hammer icon, under “spice” tab)...ive just been googling to see how to specify "alternate" solver in the ltspice schematic as a spice directive, but cant find out how to do this....thought it would be ".options alternate", but that doesn't work.I tried running the simulation and I think there must be something wrong with the controller's model. There doesn't seem to be any coherent relationship between the error amplifier output and the peak CS voltage.
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