Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Direct assignment to matrix in Verilog.

Status
Not open for further replies.

ismailov-e

Member level 1
Joined
Jan 26, 2015
Messages
34
Helped
0
Reputation
0
Reaction score
0
Trophy points
6
Activity points
295
Hi everybody!
Can we assign matrix directly like in C language.
For example:

Code Verilog - [expand]
1
2
3
reg [7:0] matrix [4:0][4:0];
 
matrix = {12345,54321,23432,55533,22212};


or

Code Verilog - [expand]
1
matrix = {{1,2,3,4,5},{5,4,3,2,1},{2,3,4,3,2},{5,5,5,3,3},{2,2,2,1,2}};



- - - Updated - - -

After Synthesis the message come: "[Synth 8-1725] cannot assign to memory matrix directly"
"[Synth 8-2833] unpacked value/target cannot be used in assignment"
 

sreevenkjan

Full Member level 5
Joined
Nov 4, 2013
Messages
268
Helped
27
Reputation
54
Reaction score
26
Trophy points
28
Location
Germany
Activity points
1,834
Hi everybody!
Can we assign matrix directly like in C language.
For example:

Code Verilog - [expand]
1
2
3
reg [7:0] matrix [4:0][4:0];
 
matrix = {12345,54321,23432,55533,22212};


or

Code Verilog - [expand]
1
matrix = {{1,2,3,4,5},{5,4,3,2,1},{2,3,4,3,2},{5,5,5,3,3},{2,2,2,1,2}};



- - - Updated - - -

After Synthesis the message come: "[Synth 8-1725] cannot assign to memory matrix directly"
"[Synth 8-2833] unpacked value/target cannot be used in assignment"

you need to refer to this thread (link below) in the edaboard forum. Check the link where a guy has asked similar question like you.

https://www.edaboard.com/thread339582.html
 

sreevenkjan

Full Member level 5
Joined
Nov 4, 2013
Messages
268
Helped
27
Reputation
54
Reaction score
26
Trophy points
28
Location
Germany
Activity points
1,834

TrickyDicky

Advanced Member level 5
Joined
Jun 7, 2010
Messages
7,025
Helped
2,058
Reputation
4,133
Reaction score
2,010
Trophy points
1,393
Activity points
38,609
mat<=((others=>(others=>'0')),(others=>(others=>'0')),(others=>(others=>'0'))); is to assign the elements in the matrix to 0 values in VHDL.

you can check the following links for verilog code as well as assigning the values into the matrix.

http://stackoverflow.com/questions/13392365/define-a-2d-array-in-verilog-a-4x4-matrix-that-storage-specific-values

http://stackoverflow.com/questions/16045332/how-to-define-and-assign-verilog-2d-arrays
The OP is asking for help with Verilog - not VHDL. DOnt answer a verilog request with VHDL examples - they are not going to help.

To the OP - try putting ' infront of the arrays:

matrix = '{ '{1,2,3,4,5}, '{5,4,3,2,1}, '{2,3,4,3,2}, '{5,5,5,3,3}, '{2,2,2,1,2}};
 

ismailov-e

Member level 1
Joined
Jan 26, 2015
Messages
34
Helped
0
Reputation
0
Reaction score
0
Trophy points
6
Activity points
295
The OP is asking for help with Verilog - not VHDL. DOnt answer a verilog request with VHDL examples - they are not going to help.

To the OP - try putting ' infront of the arrays:

matrix = '{ '{1,2,3,4,5}, '{5,4,3,2,1}, '{2,3,4,3,2}, '{5,5,5,3,3}, '{2,2,2,1,2}};
Thanks for your reply.
Is this syntax in System Verilog?
I have an error in Verilog.
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top