Direct assignment to matrix in Verilog.

[ismailov-e]

Hi everybody!
Can we assign matrix directly like in C language.
For example:

---

Code Verilog - [expand]
1
2
3
reg [7:0] matrix [4:0][4:0];
 
matrix = {12345,54321,23432,55533,22212};

---

or

---

Code Verilog - [expand]
1
matrix = {{1,2,3,4,5},{5,4,3,2,1},{2,3,4,3,2},{5,5,5,3,3},{2,2,2,1,2}};

---

- - - Updated - - -

After Synthesis the message come: "[Synth 8-1725] cannot assign to memory matrix directly"
"[Synth 8-2833] unpacked value/target cannot be used in assignment"

 

[sreevenkjan]

Hi everybody!
Can we assign matrix directly like in C language.
For example:

---

Code Verilog - [expand]
1
2
3
reg [7:0] matrix [4:0][4:0];
 
matrix = {12345,54321,23432,55533,22212};

---

or

---

Code Verilog - [expand]
1
matrix = {{1,2,3,4,5},{5,4,3,2,1},{2,3,4,3,2},{5,5,5,3,3},{2,2,2,1,2}};

---

- - - Updated - - -

After Synthesis the message come: "[Synth 8-1725] cannot assign to memory matrix directly"
"[Synth 8-2833] unpacked value/target cannot be used in assignment"

you need to refer to this thread (link below) in the edaboard forum. Check the link where a guy has asked similar question like you.

https://www.edaboard.com/threads/339582/

 

[ismailov-e]

you need to refer to this thread (link below) in the edaboard forum. Check the link where a guy has asked similar question like you.

https://www.edaboard.com/threads/339582/

Thank you. But language there is VHDL and no assignment shown.

 

[sreevenkjan]

mat<=((others=>(others=>'0')),(others=>(others=>'0')),(others=>(others=>'0'))); is to assign the elements in the matrix to 0 values in VHDL.

you can check the following links for verilog code as well as assigning the values into the matrix.

https://stackoverflow.com/questions/13392365/define-a-2d-array-in-verilog-a-4x4-matrix-that-storage-specific-values

https://stackoverflow.com/questions/16045332/how-to-define-and-assign-verilog-2d-arrays

 

[TrickyDicky]

mat<=((others=>(others=>'0')),(others=>(others=>'0')),(others=>(others=>'0'))); is to assign the elements in the matrix to 0 values in VHDL.

you can check the following links for verilog code as well as assigning the values into the matrix.

https://stackoverflow.com/questions/13392365/define-a-2d-array-in-verilog-a-4x4-matrix-that-storage-specific-values

https://stackoverflow.com/questions/16045332/how-to-define-and-assign-verilog-2d-arrays

The OP is asking for help with Verilog - not VHDL. DOnt answer a verilog request with VHDL examples - they are not going to help.

To the OP - try putting ' infront of the arrays:

matrix = '{ '{1,2,3,4,5}, '{5,4,3,2,1}, '{2,3,4,3,2}, '{5,5,5,3,3}, '{2,2,2,1,2}};

 

[ismailov-e]

The OP is asking for help with Verilog - not VHDL. DOnt answer a verilog request with VHDL examples - they are not going to help.

To the OP - try putting ' infront of the arrays:

matrix = '{ '{1,2,3,4,5}, '{5,4,3,2,1}, '{2,3,4,3,2}, '{5,5,5,3,3}, '{2,2,2,1,2}};

Thanks for your reply.
Is this syntax in System Verilog?
I have an error in Verilog.

 

[dave_59]

To use C-like array assignments, you need to be using SystemVerilog.