diode in diode connected MOS

[kavitha_rapolu]

What is the purpose of diode in this circuit?

 

[tlihu]

Keep Vdg ~= 0.7v and in saturation region, I guess.

 

[leo_o2]

I think this diode will make the NMOS gate can be charged fast and discharged much slowly.

 

[kavitha_rapolu]

Can you explain how diode will help NMOS gate to be charged up fast and discharged slowly?

 

[dick_freebird]

If this was (say) an ESD clamp, the shunt FET would have a good
"hang time" beyond where the load has discharged below a useful
Vgs.

But I would never use such a structure, its lack of "turnoff authority"
on the gate is too much uncertainty to put in my circuits.

 

[ravi_free]

here nmos Vd = Vgs + Vdiode & we are getting this 'vd' for less ckt bias current 'id'
this can be done by increase length of nmos, but may be you are gaining some area due to square law dependency of Vgs with id in saturation

 

[leo_o2]

It could not be ESD clamp because it will have current leakage always.

If this was (say) an ESD clamp, the shunt FET would have a good
"hang time" beyond where the load has discharged below a useful
Vgs.

But I would never use such a structure, its lack of "turnoff authority"
on the gate is too much uncertainty to put in my circuits.

---------- Post added at 06:09 ---------- Previous post was at 06:05 ----------

The NMOS gate is charged up fast by the current flowing from the supply, resistor and the diode. So the charging path will decide the NMOS turn-on time.
On the other hand, when supply is off, NMOS gate can't be discharged thru the diode. It can be discharged very slowly thru gate current leakage.

Can you explain how diode will help NMOS gate to be charged up fast and discharged slowly?

 

[kavitha_rapolu]

Thank you. what is the purpose of this circuit? ie having PNP transistor at the bottom?