here nmos Vd = Vgs + Vdiode & we are getting this 'vd' for less ckt bias current 'id'
this can be done by increase length of nmos, but may be you are gaining some area due to square law dependency of Vgs with id in saturation
---------- Post added at 06:09 ---------- Previous post was at 06:05 ----------
The NMOS gate is charged up fast by the current flowing from the supply, resistor and the diode. So the charging path will decide the NMOS turn-on time.
On the other hand, when supply is off, NMOS gate can't be discharged thru the diode. It can be discharged very slowly thru gate current leakage.