simce
Full Member level 4
p5210 tektronix
Maybe i sound a bit paranoic, but doing power electronic, i've seen few vaporized input stages of good DSO's and similar instruments, used to measure small signals. But sometimes happens that "small signals" to become very high. Maybe no instrument can be made to override this situations? Or maybe not? OK. For now it is not that trivial to think about this problems. We can resolve them later.
monnoliv:
I'm apsolute begginer in CPLD/FPGA designs , and this project has inspired me to start studying this technologies :idea: . So please tell me something about used FPGA in this project ( used development software, which language you are using, develpment/eval board...) so i can be in track with it!
I ment spikes with Vpp=1000V, and duration of 0.5-1s. I was unable to find what is needed current that can damage the PVT. If it is small current than U5 will be damaged.What kind of spikes? Don't forget that you have C2-R10 in parallel with U5, they act as a short for spikes, no?
Maybe i sound a bit paranoic, but doing power electronic, i've seen few vaporized input stages of good DSO's and similar instruments, used to measure small signals. But sometimes happens that "small signals" to become very high. Maybe no instrument can be made to override this situations? Or maybe not? OK. For now it is not that trivial to think about this problems. We can resolve them later.
I was thinking about U6/U7.Concerning the nonlinear capacitance of mosphet, the Idea is to have as small as possible voltage across inputs in order to have a relative constant capacitor (of +-170pf):
OK. I'm very patient person . I just want to help make this project as good as ready made DSO's, and i want make it work at first ( i hate spending time fixing stupid erros i make during develpment ).Let's work a little bit more and be patient (btw, ME proposed to me a new solution that seems vgood).
monnoliv:
I'm apsolute begginer in CPLD/FPGA designs , and this project has inspired me to start studying this technologies :idea: . So please tell me something about used FPGA in this project ( used development software, which language you are using, develpment/eval board...) so i can be in track with it!