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Yes it should be connected to AGND.simce said:U8 PIN4 (maybe to AGND)?
There is protection diodes inside the op-amp, you can read about it in the data sheet. I don't know if external capacitors are needed too, the input impedance from the BNC is quite high, 500kohm.simce said:Low capacitance protection diodes from input of amplifiers to 3v3 and GND should be added?
How big do you think they need to be?simce said:Also i think that C1 and C2 shoud be increased to get better frequency characteristic for ultra low frequencies? I know that this is not good because maximum peak current of photomos is not big enough, but!
Also i think that C1 and C2 shoud be increased to get better frequency characteristic for ultra low frequencies? I know that this is not good because maximum peak current of photomos is not big enough, but!
How big do you think they need to be?
No no, it's a mistake on the schematics website (not in the simulation, 4.7nF is the good value)....why 4.7n is used for C4 in simulation? Is this some parasitic capacitance of PVT317S?
It doesn't matter for me (simulation) but make a simulation to be sure.what about when it is set to x1 position? I think that for this configuration at least 47nF should be used. 100nF is good value by my opinion
Yes, it affect the response now, because C3 is much lower then before (in the previous revision C3 = +-250pF, thanks I didn't see the problem). As C3 is lower, 4.5pF isn't negligible anymore (0.7 dB fluctuation on BW). One have to keep in mind that the input capacitor of the buffer (say Cx) is moving from 1/2 branch to 1/200 branch depending the position switch. Anyway, I see a solution to this problem: a resistor across the capacitor (about 5 meg). It correct the problem on the 1/2 branch. On the 1/200 branch these resistor-capacitor are negligible. Of course I've to recalculate the other ladder parts to still have 1Meg/20pF input impedance.but I don't know if 4.5pF will affect the ladder, what do you think?
I'm sorry but I don't understand.monnoliv said:Yes, it affect the response now, because C3 is much lower then before (in the previous revision C3 = +-250pF, thanks I didn't see the problem). As C3 is lower, 4.5pF isn't negligible anymore (0.7 dB fluctuation on BW). One have to keep in mind that the input capacitor of the buffer (say Cx) is moving from 1/2 branch to 1/200 branch depending the position switch. Anyway, I see a solution to this problem: a resistor across the capacitor (about 5 meg). It correct the problem on the 1/2 branch. On the 1/200 branch these resistor-capacitor are negligible. Of course I've to recalculate the other ladder parts to still have 1Meg/20pF input impedance.but I don't know if 4.5pF will affect the ladder, what do you think?
monnoliv said:Hi pisoiu,
Can the trigger signal at the output of comparator be latched with the sampling clock (edge triggering on the sampling clock for example) ? Then the signal at the latch output represent an other triggering signal (delayed regarding the first one) that is synchronised with the sampling signal. If one use this second triggering signal for displaying, no more jittering will occur, no?
Regards,
Why ? 4.5pF is roughly the input capacitor of the FET buffer. If you put a 5meg resistor in parallel with this cap (then in the input of the FET buffer, between the +in and gnd) you'll have a new ladder that is frequency equilibrated (flat response). Now if you switch to the 1/200 branch, input cap + resistor are negligible comparing to 4n7 and 5K.I'm sorry but I don't understand.
The 4.5pF capacitance I was talking about is the input capacitance in the opamp, I don't think you can put 5MΩ across this capacitance??
Across which capacitor do you wan't to put 5MΩ?
That's what I was afraid you meant.monnoliv said:Why ? 4.5pF is roughly the input capacitor of the FET buffer. If you put a 5meg resistor in parallel with this cap (then in the input of the FET buffer, between the +in and gnd) you'll have a new ladder that is frequency equilibrated (flat response). Now if you switch to the 1/200 branch, input cap + resistor are negligible comparing to 4n7 and 5K.I'm sorry but I don't understand.
The 4.5pF capacitance I was talking about is the input capacitance in the opamp, I don't think you can put 5MΩ across this capacitance??
Across which capacitor do you wan't to put 5MΩ?
In fact one have to take into account also the capacitance of the GND photomos switch that is far more bigger (I didn't see it) ! One have to find something.
Good night,
No because the low impedance of other opamp (non FET) isn't well known, and we have no means to act on it.Then you might as well use an opamp with a low input resistance.
What kind of spikes? Don't forget that you have C2-R10 in parallel with U5, they act as a short for spikes, no?I think that U5 can be damaged with voltages spikes comming from input BNC (when U5 is in off state). What are your opinions about this? Also i was looking at figure 9? This is nonlinear capacitive load in input ladder.
We have to find a solution that gives at least an input stage that's equivalent to a commercial entry-level oscilloscope (and with automatic features). I think that we are not so far from the solution. One doesn't want to have a simple solution by facility, no? Let's work a little bit more and be patient :wink: (btw, ME proposed to me a new solution that seems vgood).I suggest that we make modular design of this DSO, and when we make something useful, we can change the input stage. For this, lets stay on simple input stage that contains no PVT devices and use simple switchers with low capacitance for AC/DC mode selection. In the beggining it is not that trivial to have 1mV/div. Gain of input stage can be adjusted by VGA opamp without need for switches and similar components.
Ok, I'll check.I searched a while www.analog.com and i find (by my opinion) better opamp than AD8066. I think that AD8038 is better choice. Take a look AD8038 datasheet and comment on this.
Also take a look at AD8057_8, AD8055, AD8063...