I ment spikes with Vpp=1000V, and duration of 0.5-1s. I was unable to find what is needed current that can damage the PVT. If it is small current than U5 will be damaged.What kind of spikes? Don't forget that you have C2-R10 in parallel with U5, they act as a short for spikes, no?
I was thinking about U6/U7.Concerning the nonlinear capacitance of mosphet, the Idea is to have as small as possible voltage across inputs in order to have a relative constant capacitor (of +-170pf):
OK. I'm very patient personLet's work a little bit more and be patient (btw, ME proposed to me a new solution that seems vgood).
In my opinion it's the capacitors that act as filter, depending on the way you implement the device. There are two capacitors: the first one is the one accross MOS (20pf-170pf), the second one is the input(LED)-output(MOS) capacitor (1pF).What is the BandWidth of PVT312?? I have not seen nothing in datasheet.
That's not digital lines, that's analog ones (GAINx & GND_GAINx) there are output of the DAC U10.You command the main gain with digital lines throught VGA IC.
P1 & P2 are used for the calibration...The offset calibration or compensation where are?? Is digital too??
??? Input impedance: the resistive part is 1M005 that's near 1M (and one can find the right resistors to have 1M000).Why do you change input impedance???
I'm afraid no (general purpose) instruments can sustains such voltages.Maybe no instrument can be made to override this situations? Or maybe not? OK. For now it is not that trivial to think about this problems. We can resolve them later.
So am I :lol: . Let me write you the simplest way to begin (that's my experience, not a general assertion):I'm apsolute begginer in CPLD/FPGA designs
se06745:--------------------------------------------------------------------------------
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The offset calibration or compensation where are?? Is digital too??
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P1 & P2 are used for the calibration...
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OK, But I think that isn't the best way to do it.
Yes, it support VHDL, VERILOG and AHDL (Altera proprietary langage). I've a preference in VHDL since I've a little knowledge with this langage, but I can learn VERILOG too.Does @ltera's development software supports both Verilog and VHDL? What is your preferance?
I think also that we've to use automatic offset canceling and, as you write, why not with a digital potentiometer. But take care with the price.Put a digital potenciometer with Adder OP configuration. ¿?
The Vref should be very stable.
I know that brute-force methods can last forever. I ment if there is some more efficient method?! :?:It's so dificult because the length of password can be long!!
You can find programs to fix it but needs a lot of time can be hundred of years.....
The key "ed 11 cf 2f e3" works fine if you remove the spaces: ed11cf2fe3se06745 said:Yes
I have used Advanced PDF recovery password v2.2. The key search algorithm. In three days I find a Key number 12239 that corresponds with ed 11 cf 2f e3 (hex key)
Well All ok!! But when I try to decript it with the Advanced PDF recovery password program these give me OK Decript file Succefull but not decript it. I don't know if is a bug of the program. You can try to decript it with these key.
Another program can be guaPDF but I have de DEMO program.
Best Regards!
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