digital filter RTL synthesis in verilog

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Hello all,

i am relatively new to the field of digital ASICs, but i have a working knowledge in verilog.

could someone please provide information on how a set of filter coefficients for a filter can be used to design the actual physical thing in verilog.

many thanks for your help
 

u can fix the co-effiecient values in ROM.
to release the channel beheviour.
initial channel co-efiecient value's must be get from matlab simulation.
then u can update it according the channel variation.
 

if the coeffeicients are fixed
you neednt to save the coeffeicients in rom
you can implement fixed coeffeicient multiplier in verilog
 

Is there any good Verilog Filter design examples?
 

thank u tarkyss and aravind for your valuable answers,

i sorry that my question was a bit unclear.

the filter i want to implement is to be used in an integrated ADC (fixed coefficients), so lets assume i want to implement a Decimation filter.....how do i go about implementing it in verilog?.....sounds easy to u, but not to me

so if someome can provide a nice good example, i wuld really appreciate it.

many thanks
 

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