digital error correction in pipelined adc

[manissri]

hi all,
i am desinging the 12 bit 10msps 1.5 bit piplined adc.
in which the digital error correction block is used to convert the 12 bits from 22bits. i am unable to understand the real mechanicm to this block. actullly the digital error correction is used to relax the comperator offset used in sub adc part.
if u have some pdf r docs to understand the mechanism of digiatal errro correction , plz clearyfy it ..
i understand that if there is an 1/2 lsb error in comprator then the error is take care by digital error correction block .
so how this is happening in digital error correction block
regards
manish

 

[Syukri]

pipeline used the DEC to confirm the voltage output is right....

the most critical is at the MSB bit because u have to use many regicters there ...i assume that 11 register is needed for 12 bit MSB right....

DEC not only to relax the comaparator but also as a trigger to indicate the conversion is finish and the output is ready...sound like SAR algorithm method but in pipeline se use two non-overlapping clock so in every half cycle one conversion is finish.....and this will go on continuously(after the latency)