Digital Error Correction in a 1.5 Bit Pipeline ADC

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mischivis

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I understand that digital error correction for a pipeline ADC which is based on 1.5 bit per stage
is used in order to correct offsets from comparator, opamp, etc. My question is, how does
it actually correct this offset? What is the exact mechanism that allows you to be able
to tolerate a larger comparator offset just because you have digital correction. The way I
see it, the digitial correction is just a bunch of adders!
 

mischivis said:
... how does it actually correct this offset?
What is the exact mechanism that allows you to be able to tolerate a larger comparator offset just because you have digital correction.
Click to expand...
Find here a short overview on the RSD (Redundant Signed Digit) principle: View attachment RSD-principle_overview.pdf

A comprehensive description of the RSD mechanism can be found here:
B. Ginetti, P.G.A. Jespers, and A. Vandemeulebroecke, “A CMOS 13-b cyclic RSD A/D converter”
IEEE Journal of Solid-State Circuits, vol. 27, pp. 957–964, July 1992.

mischivis said:
The way I see it, the digitial correction is just a bunch of adders!
Click to expand...
Right, see here: View attachment RSD_ to_binary_2s_complement_conversion.pdf
 
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