I did have a look at this document. This is not a simple exercise for someone with your apparent level of Verilog knowledge. This is an implementation of scalable parallel ternary CAMs, and Figure 3 is only a vast simplification of the actual block you would have to deliver. Figure 4 below it shows more of the complexity involved. This is NOT trivial. As has been pointed out above, if splitting up a bus is outside of your level of knowledge, then you will not succeed in implementing this without getting some ability in Verilog.
I've been doing this stuff for a long time and I think it would take me at least two weeks to wade through all the math, write the HDL, write a testbench and then simulate it.
Not a good choice at all for a first project.
r.b.