digital and analog co-simulation

[liusupeng]

Hi All,
I am working on digital PLL which include VCO, frequency divider, TDC, digital filter. I want to simulate the digital PLL in cadence. I have the transistor level implementation of all blocks including digital filter. If i include digital filter in the simulation using transistor level implementation, it take long time. Is there a way to include the digital filter as a gate or register level netlist instead of transistor level implementation in the simulation?

 

[rwender]

Not exactly the Cadence-specific answer you are looking for, but you can simulate these types of mixed-signal circuits quite well in CPPSIM and **broken link removed**.