This is basically to eliminate the power and ground bounce in the chips, due to rapid signal tranisitions. Having very short leads or practically no leads reduces the inductance of these pins. As the inductance is reduced, the voltage developed due to V = L(dI/dT) effect, is reduced. Also imagine, many logic pins switching simultaneously and the current flowing through the GND or VCC pins at the same time.This, would have a high di/dt, which in turn, would increase the voltage across these VCC and GND pins. As, your voltage levels are referenced to ground, this would result in the logic pins, seeing a voltage different from what it should actually be. Having multiple GND and Vcc pins, results in currents dividing between appropriate paths, reducing the voltage developed or seen at a single pin.
Check out Digital Design by John Wakerley for an effective and detailed example.