[SOLVED] Differential signals as inputs to FPGA

[Tan]

In my project,Differential signals are input to my FPGA,the output is single.Can I make use of LVDS pins to tap this issue.?

 

[FvM]

Yes, if your FPGA family support differential I/O-standards, e.g. LVDS. Review the online help or user manual of your design tool how to specify differntial pins in IO constraints,

 

[std_match]

There seems to be a fundamental difference between Altera and Xilinx about differential I/O.
In Altera, you can have a single-ended port in the top level entity and tell the place&route tools that it should be mapped to a differential transmitter/receiver.
I Xilinx, you must have both the '+' and the '-' signals as ports in the top level entity and connect them to a differential transmitter/receiver in your source code.

 

[Tan]

Thank you so much for the replies.Let me check how to use....

 

[Tan]

In lattice
LVDSIN I1 (.P_IN(IN_P), .N_IN(IN_N), .O(NODE));

where P_IN represents the positive and N_IN represents the negative polarity.

LVDSIN I1 (.P_IN(IN_P), .N_IN(IN_N), .O(NODE));
LVDSOUT I2 (.I(NODE), .P_OUT(OUT_P),.N_OUT(OUT_N));
LVDSTRI I3 (.I(NODE), .OE(OE), .P_OUT(OUT_P), .N_OUT(OUT_N));
LVDSIO I4 (.I(NODE0), .OE(OE), .O(NODE1), .P_IO(IO_P), .N_IO(IO_N));

wondering how to represent the voltage like3.3,2.5,1.8v

 

[imbichie]

If you are using lattice (i have used ECP2), then no need to map the pin_n and pin_p separately.
Means in your top design module, you need to consider only one port (positive), then in the *.lpf you need to mention that the port is LVDS.
Then automatically the negative pin will assign the inverted value.

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For lvds i think LVDS25 (2.5V), LVDS33(3.3V), etc are there, you can chose what you need (Depends upon the frequency of operation)

 

[Tan]

Great!!!..thank you...