You can't have more than one clock event in a process. You have two: 'clk' if the IF part and 'clkin' in the ELSIF part. I see what you want to do, but you are going to need a clock at twice the speed of your target data rate to create the data.
but you are going to need a clock at twice the speed of your target data rate to create the data
yes this is the solution
the fpga from xilnix only work on rising edge and differential manchester code change the output at rising and falling of clk so the solution is to make the clock speed twice than data rate