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[SOLVED] Differential Manchester::need to help to change my code

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ABO_ATHAB

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hi
i try to build Differential Manchester(https://en.wikipedia.org/wiki/Differential_Manchester_encoding) by use vhdl
this is my code but is not synthesizable:-?
i need to be synthesizable
best regards

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_logic_arith.all;


entity main is
Port (
clk,d : in STD_LOGIC;
dm : OUT std_logic );

end main;
architecture Behavioral of main is
signal temp,clkin:std_logic:='0';
begin

clkin<=not(clk);
process(clk)
begin
if(rising_edge(clk)) then

if(d='0') then
temp<=not(temp);
end if;

elsif(rising_edge(clkin)) then
temp<=not(temp);

end if;

end process;
dm<=temp;

end Behavioral;
 

bking

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You can't have more than one clock event in a process. You have two: 'clk' if the IF part and 'clkin' in the ELSIF part. I see what you want to do, but you are going to need a clock at twice the speed of your target data rate to create the data.

**

You might also look at this as an approach: http://www.ralf-hildebrandt.de/publication/pdf_dff/pde_dff.pdf
 
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ABO_ATHAB

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but you are going to need a clock at twice the speed of your target data rate to create the data



yes this is the solution
the fpga from xilnix only work on rising edge and differential manchester code change the output at rising and falling of clk so the solution is to make the clock speed twice than data rate

best regards::
m.s
 

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