Hi Sezi,
I meant the 0V, because the input PMOS can be turn on at lower potential voltage compared to NMOS.Let say the gate voltage is 0V, the source is 1.5V, so it vgs≥vth. This options can be useful like taking the input of rail-rail which will have swing from VDD to GND, even if you design for a source follower, unity gain buffer, it can be operated from 0V up the certain voltage limitation and about the applications, im not very sure about that. You may refer to other sources from net.
Regards,
Suria