Different ways of reading design in ICC

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Dan_Yang

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Hi,
I learned there are 2 ways to read designs when we do floorplan.
1. read_verilog...
2.import_designs ... ddc ..

I wonder (1)What's the difference between these two ways?
(2) initial floor plan info generated from DCT is contained in ddc, is it also contained in verilog?

So many thanks!
 

The difference is that if you follow the first way you will have to read the sdc file generated by DC, since if you imported the ddc file you won't have to do this; because ddc file has the constraints information of the design.

I don't understand the second question; DC doesn't do floorplan!
 

DC uses WLM for timing opt, and DC topology will create a virtual floorplan and uses it for opt. And the floorplan info created during DCT is stored in ddc. Did I make mistakes in understanding this ?
 

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