Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

different pulse signal using clk or syn

Status
Not open for further replies.

nil_kdm

Newbie level 1
Joined
Dec 28, 2012
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,295
i want to gen 1 us ipp pulse for every clk(which 4 khz freq by division using counter)
here program to generated the same..
these program run on simulation perfactly .
in hardware get clk but not getting 1 us pulse

please suggest me code......
and thanks for reply



library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dcm_counter is
Port ( clk1 : in STD_LOGIC;
clk : out STD_LOGIC;
ipp : out std_logic
);
end dcm_counter;
architecture Behavioral of dcm_counter is
signal count : integer :=1;
signal clk_in : std_logic :='0';
signal ipp_1 : std_logic :='0';
begin

process(clk1)
begin
if(clk1'event and clk1='1') then
count <=count+1;
if(count = 5000) then
clk_in <= not clk_in;
count <=1;
end if;
end if;
end process;
clk <= clk_in;
process(clk_in)
begin
if(falling_edge(clk_in)) then
ipp_1 <= '1','0' after 1 us;
end if;
end process;
ipp <= ipp_1;
end Behavioral;
 

naught

Member level 3
Joined
Aug 25, 2012
Messages
59
Helped
4
Reputation
8
Reaction score
4
Trophy points
1,288
Location
chengdu
Activity points
1,739
I learned from some blogs that it is better to design synchronous circuit, and to avoid use "clk_in" here to control a sequential logic.

count <=count+1; this might cause your calculator exceeds you preset...

" ipp_1 <= '1','0' after 1 us; " this line of code is not practicable in hardware, merely useful for simulation at modelsim tool.

correct me if anything wrong, thx.
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top