different output in place and route simulation and in behavioral

[qwerty_asdf]

Well in the behavioral simulation this is my output:

000000000000000000000000
000000100011100000110011
000000000000000000000000
000000100110100001100111
000000100110100101110111

While in post-route simulation I see in the output many unwanted datas (the results are included).

000000000000000000000000
000000000000000000000000
000000000000000000000000
000000000000000000000000
000000000000000000000000
000000000000000000000000
000000000000000000000000
000000000000000000000000
000000000000000000000000
000000000000000000000001
000000000000000000000011
000000000000000000010011
000000000000000000110011
000000000010000000110011
000000000010100000110011
000000000011100000110011
000000100011100000110011
000000100011100000110010
000000100011100000110000
000000100011100000100000
000000100011100000000000
000000100001100000000000
000000100001000000000000
000000100000000000000000
000000000000000000000000
000000000000000000000001
000000000000000001000001
000000000000000001000011
000000000000000001000111
000000000000000001100111
000000000010000001100111
000000000010100001100111
000000100010100001100111
000000100110100001100111
000000100110100001110111
000000100110100101110111

Where must I check for it? I do not see any strange warning..
If you need any code, i will edit my post.

I am using ISE 13.3 and I run it in Modelsim.

 

[TrickyDicky]

Are you using the same testbench?
can you post any code?

 

[qwerty_asdf]

Are you using the same testbench?
can you post any code?

Yes exaclty the same testbench.

Here is the testbench:

library IEEE;
use IEEE.std_logic_1164.all;
use STD.TEXTIO.all;
use ieee.numeric_std.all;
use work.my_package.all;

entity tb_landmark_1 is
end tb_landmark_1;


architecture TB_ARCHITECTURE of tb_landmark_1 is

file OUT_VECTORS: TEXT open WRITE_MODE is "output.txt";

component landmark_1 
		port ( 
		clk: in std_logic;
		vin:in std_logic;
		rst: in std_logic;
		dout: out std_logic_vector (23 downto 0);
		done: out std_logic
		);
end component;

signal vin: std_logic;
signal clk: std_logic;
signal rst:std_logic;
signal dout: std_logic_vector(23 downto 0);
signal done: std_logic;
signal temp_in_1: std_logic_vector(7 downto 0);
signal	temp_in_2: std_logic_vector(7 downto 0);
signal	temp_2_sq: std_logic_vector(15 downto 0);
signal	temp_2_dif: std_logic_vector(7 downto 0);
signal temp2_sum: std_logic_vector(23 downto 0);



begin

UUT: landmark_1
		port map (
			clk=>clk,
			vin=>vin,
			rst=>rst,
			dout=>dout,
			done=>done);

             
    process
        variable OUT_BUF: LINE;
       
        

   begin
       rst<='1';
        wait for 200 ns;
        rst<='0';
		vin<='1';
        wait for 200 ns;
        vin<='0';
		 wait;
    end process;
    
    process
    begin
      clk<='0';
	  wait for 50 ns;
	  clk<='1';
	  wait for 50 ns;
end process;


process(dout)
    variable OUT_BUF: LINE;
  begin
    --for q in 0 to 15 loop
			WRITE(OUT_BUF,to_bitvector(dout));
			WRITELINE(OUT_VECTORS,OUT_BUF);
		--end loop;
end process;
    
end TB_ARCHITECTURE;

and here is my .vhd file used for behavioral.
In the post route, it is used the one generated.

library IEEE;
use IEEE.STD_LOGIC_1164.all;
USE ieee.numeric_std.ALL;

use work.my_package.all;

entity landmark_1 is
  generic
		(data_length :integer := 8;
		address_length:integer:=2 ;
		comp_num:integer:=2;
		total_number:integer:=2);
		port ( clk:in std_logic;
		vin:in std_logic;
		rst:in std_logic;
		dout: out std_logic_vector(3*data_length-1 downto 0);
		done: out std_logic
		);
end landmark_1;

architecture TB_ARCHITECTURE of landmark_1 is


component ram IS
	generic
	(
		ADDRESS_WIDTH	: integer := 3;
		DATA_WIDTH	: integer := 8
	);
	port
	(
		clock			: IN  std_logic;
		data			: IN  std_logic_vector(DATA_WIDTH - 1 DOWNTO 0);
		write_address			: IN  std_logic_vector(ADDRESS_WIDTH + 1 DOWNTO 0);
		read_address			: IN  std_logic_vector(ADDRESS_WIDTH + 1 DOWNTO 0);
		we			: IN  std_logic;
		q			: OUT std_logic_vector(DATA_WIDTH - 1 DOWNTO 0)
	);
end component;

component ram2 IS
	GENERIC
	(
		ADDRESS_WIDTH	: integer := 2;
		DATA_WIDTH	: integer := 24
	);
	PORT
	(
		clock			: IN  std_logic;
		data			: IN  std_logic_vector(DATA_WIDTH - 1 DOWNTO 0);
		write_address			: IN  integer;--std_logic_vector(ADDRESS_WIDTH - 1 DOWNTO 0);
		read_address			: IN  integer;--std_logic_vector(ADDRESS_WIDTH - 1 DOWNTO 0);
		we			: IN  std_logic;
		q			: OUT std_logic_vector(DATA_WIDTH - 1 DOWNTO 0)
	);
end component;

component myrom_A IS
	port (
	clka: IN std_logic;
	rsta: IN std_logic;
	ena: IN std_logic;
	addra: IN std_logic_VECTOR(2 downto 0);
	douta: OUT std_logic_VECTOR(7 downto 0));
end component;

component myrom_B IS
	port (
	clka: IN std_logic;
	rsta: IN std_logic;
	ena: IN std_logic;
	addra: IN std_logic_VECTOR(2 downto 0);
	douta: OUT std_logic_VECTOR(7 downto 0));
end component;


signal inp1,inp2: matrix1_t(0 to address_length);
signal out_temp: std_logic_vector(data_length-1 downto 0);
signal out_temp_2: std_logic_vector(data_length-1 downto 0);
signal out_temp_3: std_logic_vector(3*data_length-1 downto 0);
signal dout_res: std_logic_vector(3*data_length-1 downto 0);
signal re_sig:std_logic;
signal address_A:std_logic_vector(address_length downto 0);
signal address_B:std_logic_vector(address_length downto 0);
signal temp_dif: std_logic_vector(data_length-1 downto 0);
signal temp_square: std_logic_vector(2*data_length-1 downto 0);
signal temp_sum: std_logic_vector(3*data_length-1 downto 0):=(others=>'0');
signal min: std_logic_vector(3*data_length-1 downto 0);
signal new_entry: std_logic;
signal i:integer range 0 to comp_num;
signal line_counter:integer range 0 to total_number*comp_num;
signal sum_counter:integer range 0 to comp_num;
signal min_counter:integer range 0 to total_number;
signal line_min_counter: integer range 0 to total_number;
signal sum_enable:std_logic;
signal sq_enable:std_logic;
signal dif_enable:std_logic;
signal done_difs:std_logic;
signal done_mins:std_logic;
signal computation_over:std_logic;
signal flag_2:std_logic;
constant offset_A: std_logic_vector(address_length downto 0) :=(others => '0' );
constant offset_B: std_logic_vector(address_length downto 0) :=(others => '0' );
constant end_of_set_B: std_logic_vector(address_length downto 0):="011";----meta na ginoun vash ton generics "101100100000000"
constant end_of_set_A: std_logic_vector(address_length downto 0):="011";
constant total_sums: integer:=total_number*comp_num;
constant last_check: integer:=total_number*total_number;
constant zero: std_logic_vector(3*data_length-1 downto 0) := (others=>'0');
constant zero_b: std_logic_vector(comp_num-1 downto 0) := (others=>'0');

signal current_start_of_A: std_logic_vector (address_length downto 0);



begin

datas_1: myrom_A port map (clk,rst,'1',address_A,out_temp);
datas_2: myrom_B port map (clk,rst,'1',address_B,out_temp_2);
write_res: ram2 generic map(ADDRESS_WIDTH=>total_number, DATA_WIDTH=>3*data_length) port map(clk,dout_res,line_min_counter,line_min_counter,re_sig,out_temp_3);
dout<=out_temp_3;
process (clk)
  
begin

if (rst='1') then 
  address_A<=offset_A;
  address_B<=offset_B;
  current_start_of_A<=offset_A;
  flag_2<='0';
  sum_enable<='0';
  sq_enable<='0';
  dif_enable<='0';
  done_difs<='0';
--else
else --(clk'event and clk='1') then
  if (clk'event and clk='1') then 
    if (computation_over='0') then
        temp_dif<=std_logic_vector(signed(out_temp)-signed(out_temp_2));
        dif_enable<='1';
         if (dif_enable='1') then
            temp_square<=std_logic_vector(resize(signed(temp_dif)*signed(temp_dif),2*data_length));
            sq_enable<='1';
         end if;
      if ((i=comp_num-1) and (done_difs='0'))  then --last item fetched, then it must reset it self.
        if (address_B=end_of_set_B) then
          address_B<=offset_B;
          if (address_A=end_of_set_A) then
            done_difs<='1';
          else 
            current_start_of_A<=std_logic_vector(unsigned(address_A)+to_unsigned(1,address_length+1));
            address_A<=std_logic_vector(unsigned(address_A)+to_unsigned(1,address_length+1));
          end if;
        else 
          address_B<=std_logic_vector(unsigned(address_B)+1);
          address_A<=current_start_of_A;
        end if;
        i<=0;
      elsif (done_difs='1') then
        address_A<=offset_A;
        address_B<=offset_B;  
        -- kanonika afta meta 8eloume na ginoun undefined me kapoio tropo 
     else
        address_B<=std_logic_vector(unsigned(address_B)+1);
        address_A<=std_logic_vector(unsigned(address_A)+1);
        i<=i+1;
      end if;-- end of =comp_num-1
	 end if; --end of done
   end if; --end of clk'event
 end if;--end of rst
end process ; 

process (clk)
  variable sum_new: std_logic_vector(3*data_length-1 downto 0):=(others=>'0');
  begin
if (rst='1') then 
    sum_counter<=0;
    temp_sum<=zero;
    computation_over<='0';
    line_counter<=0;
else 
  if (clk'event and clk='1') then 
    if (computation_over='0') then
    if (sq_enable='1') then
      if (sum_counter=comp_num-1) then
        --temp_sum<=temp_sum+resize(temp_square,3*data_length);
        sum_new:=std_logic_vector(signed(sum_new)+resize(signed(temp_square),3*data_length));
        temp_sum<=sum_new;
        new_entry<='1';
        sum_counter<=0;
        if (line_counter= total_sums) then
          computation_over<='1';
      end if;
     else 
        sum_counter<=sum_counter+1;
        new_entry<='0';
        if (sum_counter=0)then
          --temp_sum<=resize(temp_square,3*data_length);
          line_counter<=line_counter+1;
          sum_new:=std_logic_vector(resize(signed(temp_square),3*data_length));
          temp_sum<=sum_new;
        else
        --temp_sum<=temp_sum+resize(temp_square,3*data_length);
        sum_new:=std_logic_vector(signed(sum_new)+resize(signed(temp_square),3*data_length));
        temp_sum<=sum_new;
       end if;
     end if;--end of sum counter
   end if;--end of sq enable
  end if; -- end of computation over
 end if; --end of clk
end if; -- end of rst
end process;

process (clk)
  begin
if (rst='1') then
  --exit_counter<=0;
  re_sig<='0';
  min_counter<=0;
  line_min_counter<=0;
  min<=zero;
  done_mins<='0';
  done<='0';
else
  if (clk'event and clk='1') then 
    if (done_mins='0') then
    if (new_entry='1') then
      --- minimum function
      if (min_counter=0) then
         re_sig<='0';
         min<=temp_sum;  
         min_counter<=min_counter+1;
      else
         if (min_counter=total_number-1) then-- result of this is min
           re_sig<='1';
            if (temp_sum<min) then 
              min<=temp_sum;
              dout_res<=temp_sum;
           else
              dout_res<=min;
            end if;
           --dout_res<=min;
           min_counter<=0;
            if (line_min_counter=total_number) then
              done_mins<='1';
            else
              line_min_counter<=line_min_counter+1;
            end if;
         else
          re_sig<='0';
          min_counter<=min_counter+1;
         end if;
      end if;
    end if;--end of new_entry
   else
     done<='1';
   end if;--end of done
  end if; --end of clk
end if;--end of rst
end process;

end TB_ARCHITECTURE;