Refer to Library Compiler & Design Compiler & Power Compiler for more details ...
The simplest explaination is : Library is nothing but a dat bank where you can pick up the essential information for your design ..
Synthesis tools work in a number of stages. One stage is where the purely logical equations derived from the RTL are "mapped" to a target library. "Mapping" is the translation from logical operators to a set of actual gates that implement that function.
Every library is different: each has a different set of cells, the timing characteristics of the cells are unique to each library, etc.
Refer to Library Compiler & Design Compiler & Power Compiler for more details ...
The simplest explaination is : Library is nothing but a dat bank where you can pick up the essential information for your design ..
Hi
I need to synthesis my file but I don't have 0.18um and 0.13um TSMC or SMIC or CMOS.
If possible, I send u my file and u synthesis It. Do u do it?
Thanks.