Once currents enter a "port", how they may divide and sum
is not "visible" to the graphical design system. Maybe if
you knew all the subcircuit nodes / elements' naming,
you could dig deeper in Spectre. But the intermediate
netlist you see, is not the "real deal" - only the outer skin,
so to speak.
The current that is returned to Spectre, can be mapped
to an element within the FET, you see it as a primitive
but it is not necessarily so - it can be a composite with the
details hidden from view, and not all currents will be reported.
But a simple element (resistor, voltage source, presistor)
has a simple / believable port result, and presistor has the
nice feature that it does not bugger LVS later.
Not really a concern in your present schematic (the voltage
sources serve just as well) but in a more complex circuit
that will proceed to layout, you don't want a bunch of things-
that-will-not-be-present in the schematic to mess up your
netlist match.