differences between various xilinx family in synthesis

[ya_montazar]

Hi,
I have synthesized one design in three different family of xilinx and they have 3 different result in synthesis report and using resources.
I know some differences between various xilinx family resources, but the results of using them in my project differ tremendously in 3 type of xilinx family: virtex4 with two others: ZYNQ , Virtex7.
I can not undrestand the reason of this.
here you see the reports:

 

[TrickyDicky]

There certainly appears to be a problem with the Virtex 4 build - theres hardly anything there. are the sure the project is identical for all 3 builds?

Other differences are because of different algorithms and the base logic. So there is always going to be differences between families.

 

[ya_montazar]

absolutely!
the only my mistake was the digital clock manager that differs to others which I have refine it.
again the result was about same.