Difference Between VHDL and Verilog?

[ramagandhi]

Hi all,
Please tell me difference between VHDL and VERILOG and using application area of both.
Thanks.

 

[OhaAmo]

Generally they are both the same with minor changes, using for same applications. Verilog is a lot common in the industry than VHDL.

 

[dave_59]

If you look at the synthesizable subset of both languages, they are very similar in capabilities, but code written in Verilog will have much better performance than the same code written in VHDL. Verilog was much more popular for larger ASIC designs, which had performance and capacity demands on their simulations that FPGA designs did not. So geographical areas where ASIC design was more popular will also be where Verilog will be more popular.

For the rest of the non-synthesizable portion of the two languages, VHDL certainly had more capabilities than Verilog, but SystemVerilog borrowed a lot from VHDL and is now the predominant language for writing testbenches.

 

[ramagandhi]

Thanqs dava_59