Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
If you look at the synthesizable subset of both languages, they are very similar in capabilities, but code written in Verilog will have much better performance than the same code written in VHDL. Verilog was much more popular for larger ASIC designs, which had performance and capacity demands on their simulations that FPGA designs did not. So geographical areas where ASIC design was more popular will also be where Verilog will be more popular.
For the rest of the non-synthesizable portion of the two languages, VHDL certainly had more capabilities than Verilog, but SystemVerilog borrowed a lot from VHDL and is now the predominant language for writing testbenches.