Difference Between these Piece's of Verilog Code.

[mail4idle2]

Differences in Synthesis and Simulation between below codes.
Difference is
1st piece of code BLOCKING STATEMENT
RightShift = RightShift & Strobe;
2nd piece of code NON BLOCKING STATEMENT
RightShift <= RightShift & Strobe;


module test (
ClockB,
Strobe,
Xflag,
Mask,
RightShift,
SelectFirst,
CheckStop
);

input ClockB, Strobe, Xflag, Mask;
output RightShift, SelectFirst, CheckStop;
reg RightShift, SelectFirst, CheckStop;

always @ (negedge ClockB)
begin
RightShift = RightShift & Strobe;
SelectFirst <= RightShift | Xflag;
CheckStop <= SelectFirst ^ Mask;
end


endmodule

#################################################################################

module test (
ClockB,
Strobe,
Xflag,
Mask,
RightShift,
SelectFirst,
CheckStop
);

input ClockB, Strobe, Xflag, Mask;
output RightShift, SelectFirst, CheckStop;
reg RightShift, SelectFirst, CheckStop;

always @ (negedge ClockB)
begin
RightShift <= RightShift & Strobe;
SelectFirst <= RightShift | Xflag;
CheckStop <= SelectFirst ^ Mask;
end


endmodule

##############################################

 

[FvM]

Simulation consistencies are caused by not initializing registers, but not related to blocking versus non-blocking I think. Part of the code is pretty useless, RightShift won't be ever set.

I believe that most has been said about blocking versus non-blocking in the classical Cummings paper. See https://www.edaboard.com/threads/175727/#post737345

 

[mail4idle2]

Does synthesis system realize 3 registers in each case ?

 

[FvM]

Does synthesis system realize 3 registers in each case ?

Two registers and identical netlist for both cases, because RightShift is discarded in synthesis. You should chose meaningful code to demonstrate effect of blocking assignments.

 

[mail4idle2]

It synthesis and gets three registers as RightShift is defined as output in both scenarios