Simulation uses software models to validate the design. The library model characteristics (propagation delay, setup/hold time, etc.), for example, are usually very close to the real silicon. Simulation provide a great control environment for debug (you have visibility to all the signals) but has poor run-time speed.
Emulation do not use any models. The actual design is synthesis/par for the targeted FPGA in the emulation board. Emulation provide excellent run-time speed (up to full clock speed) but poor debugging support (can't see inside the FPGA really). Usually emulation is used when you're designing a complex ASIC and want to have a more confidence level that the chip doesn't have any bugs. With at-speed emulation testing, you can uncover many hard to catch corner-case bugs that simulation can't. For example, 1 sec of simulation time will take weeks to complete, whereas, it will take 1 sec in emulation.
- Hung