ASIC_intl said:What are the differences betwwen net (e.g. wire) and register in verilog. I know that register can store the value until or unless another value replaces them. But net also has same property.
Is the following syntax acceptable inside a verilog module?
wire a;
initial
begin
a = 1'b0;
end
ASIC_intl said:Hi pini_1
But nets can also store values as reg can.
We can declasre the following statement:
wire a_name = 1'b0.
So wire here is storing the value logic zero.
Again in a code of mux in Verilog in behavioral we declare the output as reg. But in a mux there is no necessity of the output to store the value. The dataflow description of a mux for the same reason do not need to declare the output as reg.
ASIC_intl said:Hi pini_1
But nets can also store values as reg can.
We can declasre the following statement:
wire a_name = 1'b0.
So wire here is storing the value logic zero.
Again in a code of mux in Verilog in behavioral we declare the output as reg. But in a mux there is no necessity of the output to store the value. The dataflow description of a mux for the same reason do not need to declare the output as reg.
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