praveersaxena
Newbie level 6
sir,actually i m working of adiabatic cmos logic.
actually i m confused with conventional ADCL logic and Modified ADCL LOGIC.
Suppose i m charging a capacitor by a sinusoidal source through a path with Diode -MOS COMBINATION. WITH p TERMINAL OF DIODE IS CONNECTED TO sinusoidal souce and its N terminal is connected to source of a pmos and whose drain is connected to capacitor AND GATE OF PMOS IS CONNECTED TO 0 VOLTS . I.E. LOGIC 0.
will it show different characteristics if we interchange the position of pmos and diode, with pmos connected to sinusoidal source and its drain connected to p terminal of diode whose n terminal is connected to capacitor.
what will be effect on power dissipation, delay.
plz provide this guidance. thnks
regards
actually i m confused with conventional ADCL logic and Modified ADCL LOGIC.
Suppose i m charging a capacitor by a sinusoidal source through a path with Diode -MOS COMBINATION. WITH p TERMINAL OF DIODE IS CONNECTED TO sinusoidal souce and its N terminal is connected to source of a pmos and whose drain is connected to capacitor AND GATE OF PMOS IS CONNECTED TO 0 VOLTS . I.E. LOGIC 0.
will it show different characteristics if we interchange the position of pmos and diode, with pmos connected to sinusoidal source and its drain connected to p terminal of diode whose n terminal is connected to capacitor.
what will be effect on power dissipation, delay.
plz provide this guidance. thnks
regards
