Difference between output datarate and sampling frequency in ADC- MAX1415

[aashishsharma]

Hi I am using 16 bit ADC Max1415. It boast of sampling rate of fckin/64MHz. I am using internal clock with 2.4576Mhz so sampling rate becomes 38.4 Khz. but output data rate as mentioned in the datasheet is 60Hz. I figured out code and everything for that ADC but at my end I am finally getting just 2 samples per second.
I dont think arduino code which I am using can create that much delay. So what does sampling rate means if we are not getting data at that rate?
thanks in advance

 

[barry]

That device has a filter in it which allows you to program the output data rate (which has nothing to do with the sample rate).

 

[aashishsharma]

but if output data rate is say 60Hz which means its giving 60 output per sec.
And sampling rate is too high? you are referring that output here is not the output of ADC?
And if yes then why ADC is so slow ie only 2 samples per sec when it should give higher

 

[barry]

You need to educate yourself about multi-rate filters, decimation, and such. If you are sampling at 1K-samples/second, and you output every tenth sample your output rate is 100 samples/sec. If you output every hundredth sample, your data rate is 10 samples/second. In either case your SAMPLE rate is 1K samples/sec.

 

[aashishsharma]

okay that means even if my sample rate is say 1khz maximum frequency signal I can get by sampling using adc is nto 500hz(nyquist criteria) but would depend upon output rate?
As I am only to reconstruct frequency upto 1-5 Hz

 

[barry]

I'm not sure I understand your question, but if you have no decimation, your output rate will equal your sample rate. You apparently are using a device you don't understand.

It has a multi-rate filter.
It is reducing your output data rate.
If you want a higher output data rate, program the ADC properly.

 

[aashishsharma]

Hey I got it. If I want output datarate to be equal to sampling rate I need to have no decimation atall. But I cant find any option to do so in ADC datasheet. FS0 FS1 bits in clock register controls decimation and minimum I can have is 38 which is giving me output of 500 samples per sec according to datasheet. I did that and indeed I am getting 1000 samples in 3 seconds
How can I disable decimation altogether?

 

[barry]

Sorry, but from the datasheet it looks like your stuck with a minimum decimation of 38.

 

[aashishsharma]

then there is no way I can sample signal greater than 250 Hz according to nyquist criteria right? as decimation rate of 38 gives me 500 samples per sec. I dont think then there is any use of boasting in there datasheet about high sampling rate?

 

[FvM]

then there is no way I can sample signal greater than 250 Hz according to nyquist criteria right? as decimation rate of 38 gives me 500 samples per sec. I dont think then there is any use of boasting in there datasheet about high sampling rate?

Input sampling rate is a technical detail information, dedicated to readers with basic knowledge about oversampling ADCs. If you don't want to get bothered with it, there's also a clear specification of achievable output data rates and signal filtering. And detailed background information about sigma-delta method if you are willing to learn.

Did you realize that the input signal is already considerably attenuated at the nyquist frequency related to the output data rate. For the suppresion of unwanted frequency components you can nevertheless rely on the high input sampling frequency.

 

[aashishsharma]

Does than mean this max1415 is good only for signals less than 250 hz right?
There is no way i can use it to sample say 1khz sine wave?

 

[barry]

No.


The datasheet says the sample rate is fin/64. For a 1MHz clock, that's 15.625KHz sample rate. And your maximum output rate is 411 samples/sec.

 

[aashishsharma]

That would be even less than this as in datsheet they are further dividing it by 128 in formulae specified. Maximium theoritical output rate is 500 samples per sec only
Any 16 bit differential adc with 2 channels having atleast 1khz sampling rate and preferably dip package

 

[barry]

That would be even less than this as in datsheet they are further dividing it by 128 in formulae specified. Maximium theoritical output rate is 500 samples per sec only
Any 16 bit differential adc with 2 channels having atleast 1khz sampling rate and preferably dip package

Analog Devices has about 50 of them that meet that requirement. I'm sure TI, Maxim, etc., do too.

Try looking on the mfrs. sites.