lin134340
Newbie level 4
Hello,
In layout design, high voltage device must be generated in high voltage well.
I want to know what's the difference between high voltage n-well and an normal n-well.
The reason why I want to know that is..... In a project, we use SMIC 0.18um technology. In it's DRC rule, it shows that layer NW is n-well for 3.3V/1.8V device while layer NWH is HV n-well.
When generate a 5V device, we should use NWH for it. But the mistake is we draw both NWH and NW for it.(the 5V device are surrounded by both NW and NWH) There is no DRC error for it, so we don't check out the mistake.
What's the difference between high voltage n-well and an normal n-well?Does this error matters? Is it a critical error?
In layout design, high voltage device must be generated in high voltage well.
I want to know what's the difference between high voltage n-well and an normal n-well.
The reason why I want to know that is..... In a project, we use SMIC 0.18um technology. In it's DRC rule, it shows that layer NW is n-well for 3.3V/1.8V device while layer NWH is HV n-well.
When generate a 5V device, we should use NWH for it. But the mistake is we draw both NWH and NW for it.(the 5V device are surrounded by both NW and NWH) There is no DRC error for it, so we don't check out the mistake.
What's the difference between high voltage n-well and an normal n-well?Does this error matters? Is it a critical error?