Difference between makefile , tcl , bash , perl

[fahum]

Hi ,

Can somebody summarize the difference between makefile, tcl , bash , perl scripts ... (i mean in the concept and use not the syntax) when to use which ? can one type replace the other ? sorry if it's a beginner's question

 

[sky_123]

They are all scripting/programming languages (well bash is an interpreter). At a high level they all do the same thing, i.e. allow you to do things programatically.
In real world use-cases, people tend to use them for different things, sometimes due to convention, sometimes due to the environment (e.g. bash is often
useful for Linux environments, but not always necessarily for a windows environment).
makefiles are often ideal for organizing your steps to build your app (e.g. compile, link, etc). tcl is ideal for writing modules of arbitrary code, maybe for extending an
existing app for instance, or writing a complete app. Perl does a similar thing, but has some strengths for character manipulation. bash is an interpreter, but you can
write scripts for that too. Again, these are essentially instructions. Often used to set up an environment for (say) coding or for (say) beginning your testing, etc.

 

[nav_vlsi]

For Example, if you wanted automate your synthesis flow. you could do something this.

1. use make & create a make target for synthesis - this would run the entire set of commands to be run for synthesis.

2. Perl - any post or pre processing required for the make target (here synthesis) can be run using perl . typically any wrapper around tools would normally written in perl (this is not a generic comment but base don my own exp)

2. TCL - once u invoked the EDA tool inside make flow , and you wanted to run extra routines like multiple optimization scenarios within EDA environment , they we could use TCL.

to summarize ,
MAKE for flow automation ,
PERL for any wrapper over EDA tools &
TCL for any routines inside EDA tool Environment.
(this is not a generic comment but base don my own exp)

-Nav

 

[rocking_vlsi]

As VLSI Design Engineer or Verification Engineer, it is good to get know about all these languages

1) Makefile :- to make target, for example you want to invoke tool (design compiler or VCS) from shell and provide some additional while invoking tools such -f source.f

2) Perl: Basically used for processing large text files. For example after generating large report, you want to divide in many parts.

3) TCL : Most of the time it is used supply values or set attributes to tools like DC and VCS while they are running.