A Flip-Flop is normally edge triggered into one of two states:
Clock and Data input (D type 74HC74,74HC574)
OR
Combination of Set, Reset, Clock & Data (Master/Slave J-K type 74HC73)
A Flip-Flip cannot be transparent
A Set-Reset Latch output is edge triggered on or off by Set/Reset inputs.
A Transparent Latch
The Output will follow the Input (transparent) until the control input 'freezes/latches' the Output (latched condition).
It is Level controlled not edge triggered. (74HC373/573)