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If you have Verilog or VHDL code for ASIC, of course you can modify it for use with FPGA. But, the amount of modifications can be large enough. The problems include:
1) FPGA doesn't support clock gating (althought some tools, like Synplify, can "emulate" it).
2) Library elements for all RAMs, I/O pads etc. should be changed to the corresponding elements from FPGA library.
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