difference between always and assign in verilog

[vead]

I am confused I want to know what is difference between always and assign and where they use

program 1st

---

Code Verilog - [expand]
1
2
3
4
5
module and2gate (A,B,Y);
input A,B;
output Y;
assign Y=A&B;
endmodule

---

program 2st

---

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
module and2gate (A,B,Y);
input A,B;
output Y
reg y
always@(AorB);
begin
Y<=A&B;
end
endmodule

---

which program is right please someone explain where we use always and assign syntax

 

[ads-ee]

Here is a good discussion on the subject.
https://groups.google.com/forum/m/#!topic/comp.lang.verilog/3KSGBkVOSLU

 

[vead]

Here is a good discussion on the subject.
https://groups.google.com/forum/m/#!topic/comp.lang.verilog/3KSGBkVOSLU

I think assign is used for combination logic and always is used for sequential logic please clear my doubt

 

[dave_59]

An assign statement is usually used for combinational logic.Of course, if your technology allows it, you could model a latch or sequential logic out of a combinational feedback loop. But that is very rare.

An always block can readily be used for either. Whether it is combinational or sequential depends on how you trigger the execution of the block, as well as ordering of reads versus writes to variables within the same block and between different blocks. So a single always block could represent both kinds of logic at the same time.

SystemVerilog added three flavors of always blocks: always_comb, always_latch, and always_ff, to specify your intent and to report when what you've modeled doesn't match the intent.

 

[vead]

I have posted two program which one is right

 

[sss-90]

the second one is right

 

[dave_59]

They are both functionally correct, except that you should not use '<= non-blocing assignment operators with combinational logic.

 

[ftsolutions]

+1 with dave_59. One very often does have non-blocking assignments within an always@ block because the block is generally executed on a clock or signal transition and not continuously.
An assign statement within a module is always/continuously made within the module.
If you don't need to qualify your combinational logic with synchronizing to a clock edge or other signal transition, it is generally preferred (to me anyway) to implement the combinational logic with the assign statement.

 

[FvM]

In the present example, the continuous assignment variant seems preferable already by it's conciseness. A behavioral modelling style and procedural assignments are often suitable for complex combinational logic, using e.g. conditional, case and looping statements.

Behavioral constructs, either for combinational or registered logic, involve much of the elegance and coding efficiency of Verilog or VHDL.