Re: difference b/w contention latency and serializtion laten
I can't help you with contention or serialization latency, but latency is a much overloaded term in electronic design.
Another set of latencies you need to consider are clock source latency and clock network latency. Clock source latency is the delay between the clock signal starting at some imagined source off-chip to it arriving at the starting pin visible in your design. This is important if you want to set the phase relation between two clocks.
Clock network latency is the time delay between the root pin of the clock signal and the clock pins on the flip-flops. This corresponds to the insertion delay in propagated clock mode. This is important for top-down design where you want to specify the clock delays because you need all the branches in different sub-blocks to be balanced when they are all connected together by the top-level master clock.