A Fifo is usual a dual-port RAM and includes two counters to point to the write and read addresses and some logic to indicate the FIFO status.
The dual port RAM in the case of synchronous FIFO and it can be quite harder in the case of async. FIFO
I was talking about the internal structure of Fifo of course everybody knows there is no address lines in FIFO, I think of it as a circled RAM with two counters
watever is said above is correct. I just want to add that "A FIFO doesn't provide u access to any random location i.e. its strictly on First In First Out basis, whereas a RAM has address lines so u can access any random location"
also FIFO is implemented using Dual Port Ram as said above