[DFT] Why chain test pattern is required?

[maulin sheth]

Hello All,

Can any one brief me about why we require chain test pattern during ATPG/pattern simulation?
And what will happen if we dont generate it?

Thanks & Regards,
Maulin

 

[maulin sheth]

[DFT] Power reduction in chain test

Hello All,

Can any one brief me about power reduction techniques we can do for chain test pattern?
And what are the switches that takes care power reduction in cadence Encounter True time ATPG.

Thanks & Regards,
Maulin

 

[ssd1692]

chain test pattern is required to test scan chain integrity. That is to see if the scan chain is not broken ( can be due to some drc violation during insertion or there might be fault on shift path in real silicon ) and can correctly shift values. It is a test which must be done.