Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

DFT scan insertion querry

Status
Not open for further replies.

abc_81

Junior Member level 2
Joined
Jul 6, 2009
Messages
23
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
bangalore
Activity points
1,421
Hi ,
I am working on scan insertion. I have some querries on the same.
My understanding is lockup latch is not needed when we have negedge flop followed by pos edge flop. But when we have pos edge flop followed by neg edge flop, can I use lockup latch between pos edge -> lockup latch -> neg edge ? Will this work ?
or lockup latches are used only between cross clock paths ? Please clarify
 

abc_81

Junior Member level 2
Joined
Jul 6, 2009
Messages
23
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
bangalore
Activity points
1,421
to be specific, I wanted to know if we can use lockup latch between pos edge flop and neg edge flop in a single scan chain or lockup latch should be used only between different clock domain ?
 

englishdogg

Full Member level 5
Joined
Jan 10, 2012
Messages
250
Helped
38
Reputation
76
Reaction score
40
Trophy points
1,308
Location
India
Activity points
2,742
Yes, you can use LuL in single scan chain when your mixing edges as well
 

Gayathri Jeyaram

Junior Member level 1
Joined
Jul 30, 2012
Messages
16
Helped
4
Reputation
8
Reaction score
4
Trophy points
1,283
Activity points
1,375
Hi ,
I am working on scan insertion. I have some querries on the same.
My understanding is lockup latch is not needed when we have negedge flop followed by pos edge flop. But when we have pos edge flop followed by neg edge flop, can I use lockup latch between pos edge -> lockup latch -> neg edge ? Will this work ?
or lockup latches are used only between cross clock paths ? Please clarify

Hey,

Lockup latch are used as a synchroniser between two flop from different clock domains (asynchronous clocks) along the scan chain and add in the SI path.

There is a switch in RTL complier to mix compatible clocks in a scan chain for posedge negedge launch capture and if they are of synchronous clock same frequency or frequency as a multiple of the same number, you can apply a multicycle path exception while timing them.
 

englishdogg

Full Member level 5
Joined
Jan 10, 2012
Messages
250
Helped
38
Reputation
76
Reaction score
40
Trophy points
1,308
Location
India
Activity points
2,742
i think the query here is not on mixing clock domains but for same clock domain if there are pos and neg edges if a LuL will be added in a single chain.
This is what i understood and yes this is possible as well.

Although in such a case it is good to have all neg flops together and all osedge flops together and then have them in a single scan chain with this we can have the a control on the LuL that will be added
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top