DFT Questions and FPGA based design

[kiranks9]

DFT Questions

1)Is it recommend to have tri-state bus in the design, if so what precaution needs to be taken during design

2)Functionally it is taken care that the existing tri-state bus drivers can never create bus contention. Is this sufficient for Scan shift and capture? Do we need to take any extra care? Why?

3)If the entire design is a shift register, do you need scan insertion, explain

4)How do you ignore the block which is already scan inserted from re-inserting scan?

5)What is the purpose of latches at the end of scan chains and is there any impact, explain

 

[santhosh007]

Re: DFT Questions

1)Is it recommend to have tri-state bus in the design, if so what precaution needs to be taken during design

you need to make sure that there will not be contention on the tristate drivers during shift.

2)Functionally it is taken care that the existing tri-state bus drivers can never create bus contention. Is this sufficient for Scan shift and capture? Do we need to take any extra care? Why?

if its taken care for the test mode also then no issues.

3)If the entire design is a shift register, do you need scan insertion, explain

I think this may not be the case. if it is no need of the scan. bcoz you just shift the data as many cycles as shift registers and check the results.

4)How do you ignore the block which is already scan inserted from re-inserting scan?
you have option in scan insertion tools to define your existing scan chain details and connect them with some other module or top level

5)What is the purpose of latches at the end of scan chains and is there any impact, explain

lock up latches at the scan out will provide you the half cycle hold time margin, so that you can avoid the potnetial timing delays @ the output or if these chains are connected to some other chains the same way it will be useful.

 

[gbaerf]

DFT Questions

hi ,

I am a bigginer please tell me at which state DFT is needed in FPGA based design and what are the tools those addresses these problems

With Regards,

 

[santhosh007]

Re: DFT Questions

there is no concept of DFT in FPGA based designs. Bcoz it is already manufactred the silicon(FPGA), all you are going to do is mapping your desogn with existing available gates.

 

[gbaerf]

DFT Questions

then when does we need to do DFT and Why ???

Pls answer

 

[santhosh007]

DFT Questions

DFT activites invloved in the ASIC flow after synthesis is done.

During Actual FPGA manufacturing, DFT activities are there.